A high-integrity computing environment may execute critical applications with an undetected fault rate smaller than an integrity specification that may be selected based on the demands of the critical applications. Further, high-integrity computing environments may typically be designed such that integrity-monitoring processes are transparent to the application software for compatibility and ease of application development. It may be desirable in many applications to develop high-integrity computing environments using Commercial off-the-shelf (COTS) devices to limit costs and leverage innovations in processing architectures. However, COTS device vendors are increasingly moving away from computing environments with discrete host processors towards highly-integrated multi-core system-on-chip (SoC) devices in which system performance, rather than determinism of a particular computation, is a primary design goal. For example, multi-core SoCs may not expose low-level busses for transparent access to processor computations and/or may feature asynchronous hardware events such as, but not limited to, asynchronous internal clock domain crossings, divergent branch predictions, translation lookaside buffer/cache states, or multi-core interference channel latency jitter. Further, multi-core SoCs may utilize internal scheduling to reorder and/or parallelize the execution of an input instruction set, which may impact the design of an integrity monitoring process. Multi-core SoCs may thus present challenges for the development of high-integrity computing environments using COTS devices that are transparent to the application software.